High-speed semiconductor devices are complex and contain thousands or even millions of circuit elements, such as transistors, logic circuits, and the like. When a large number of circuits are switched to different logic states, the power supply providing power and ground signals to the circuits is momentarily stressed by the sudden increase in electrical current. The momentary degradation in supply voltage, caused by the rapid switching of a large number of circuits, can cause performance degradation in the semiconductor device. For example the increased line noise created by a power supply fluctuation can cause a loss in signal transmission speed, rise time degradation, and false switching of logic gates.
To avoid a drop in the power supply voltage, caused by the rapid switching of a large number of circuits, a common practice is to include a bypass capacitor to stabilize current surges, and to avoid a momentary drop in power supply voltage. In low-frequency devices, bypass capacitors are incorporated into the package housing of the semiconductor device; or alternatively, the bypass capacitors are located completely external to the device package and are mounted on a printed circuit board. Although bypass capacitors mounted in either the device package or on the circuit board are effective in reducing performance degradation of semiconductor devices operating at low frequency, the self-inductance and line inductance incurred by using remotely located bypass capacitors is too great for high-performance devices operating at high frequencies. Thus, the line inductance and the capacitor self-inductance limits the use of external capacitors for high speed devices.
To reduce the length of the interconnections between the bypass capacitor and the device, which also reduces the line inductance, bypass capacitors are mounted directly to the upper surface of the semiconductor device. A close-attached-capacitor (CAC) can be used to reduce the length of interconnections and hence the line inductance to the capacitor. This technique is described in U.S. Pat. No. 5,049,979 to S. H. Hashemi, et al., issued Sep. 17, 1991. By mounting the bypass capacitor directly to the upper surface of the semiconductor device, the line inductance between the capacitor and the device is substantially reduced. The lower inductance reduces the AC voltage noise induced by the capacitor in the power distribution network of the device as the logic circuits rapidly switch on and off.
Although the CAC improves the operation of a high-performance semiconductor device by reducing line inductance, the CAC itself continues to have a large amount of internal inductance. The high internal inductance of the CAC is similar to that of bypass capacitors mounted in the device package, and on a printed circuit board. These capacitors have a large surface area, yet are internally constructed in such a way as to generate high internal inductance. Accordingly, further development of CAC type bypass capacitors is necessary to meet the performance requirements of high-speed semiconductor devices.